COMPROF and COMPLACE: shared-memory communication profiling and automated thread placement via dynamic binary instrumentation

TY - GEN

T1 - COMPROF and COMPLACE

T2 - 29th IEEE International Conference on High Performance Computing, Data, and Analytics

AU - Kirkpatrick, Ryan

AU - Brown, Christopher

AU - Janjic, Vladimir

N1 - This work was generously supported by UK EPSRC Energise, grant number EP/V006290/1.

PY - 2023/4/26

Y1 - 2023/4/26

N2 - This paper presents COMPROF and COMPLACE, a novel profiling tool and thread placement technique for shared-memory architectures that requires no recompilation or user intervention. We use dynamic binary instrumentation to intercept memory operations and estimate inter-thread communication overhead, deriving (and possibly visualising) a communication graph of data-sharing between threads. We then use this graph to map threads to cores in order to optimise memory traffic through the memory system. Different paths through a system's memory hierarchy have different latency, throughput and energy properties, COMPLACE exploits this heterogeneity to provide automatic performance and energy improvements for multi-threaded programs. We demonstrate COMPLACE on the NAS Parallel Benchmark (NPB) suite where, using our technique, we are able to achieve improvements of up to 12% in the execution time and up to 10% in the energy consumption (compared to default Linux scheduling) while not requiring any modification or recompilation of the application code.

AB - This paper presents COMPROF and COMPLACE, a novel profiling tool and thread placement technique for shared-memory architectures that requires no recompilation or user intervention. We use dynamic binary instrumentation to intercept memory operations and estimate inter-thread communication overhead, deriving (and possibly visualising) a communication graph of data-sharing between threads. We then use this graph to map threads to cores in order to optimise memory traffic through the memory system. Different paths through a system's memory hierarchy have different latency, throughput and energy properties, COMPLACE exploits this heterogeneity to provide automatic performance and energy improvements for multi-threaded programs. We demonstrate COMPLACE on the NAS Parallel Benchmark (NPB) suite where, using our technique, we are able to achieve improvements of up to 12% in the execution time and up to 10% in the energy consumption (compared to default Linux scheduling) while not requiring any modification or recompilation of the application code.

KW - NUMA

KW - Thread Placement

KW - Data Placement

KW - Cache Optimisation

KW - Energy Optimization

KW - Refactoring

KW - QA75 Electronic computers

KW - Computer science

KW - NDAS

KW - Energy Optimisation

UR - https://www.scopus.com/pages/publications/85158089521

U2 - 10.1109/HiPC56025.2022.00040

DO - 10.1109/HiPC56025.2022.00040

M3 - Conference contribution

SN - 9781665494243

T3 - International Conference on High Performance Computing, Data, and Analytics (HiPC)

SP - 236

EP - 245

BT - 2022 IEEE 29th International Conference on High Performance Computing, Data, and Analytics (HiPC)

PB - IEEE

CY - Bengaluru, India

Y2 - 18 December 2022 through 21 December 2022

ER -