Electrical test structures for investigating the effects of optical proximity correction

A. Tsiamis, S. Smith, J.T.M. Stevenson, A.J. Walton, M. McCallum, A.C. Hourd

    Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

    2 Citations (Scopus)

    Abstract

    Electrical test structures have been designed to enable the characterisation of corner serif forms of optical proximity correction. These structures measure the resistance of a conducting track with a right angled corner. Varying amounts of OPC have been applied to the outer and inner corners of the feature and the effect on the resistance of the track investigated. A prototype test mask has been fabricated which contains test structures suitable for onmask electrical measurement. The same mask was used to print the structures using an i-line lithography tool for onwafer characterisation. Results from the structures at wafer level have shown that OPC has an impact on the final printed features. In particular the level of corner rounding is dependent upon the dimensions of the OPC features employed and the measured resistance can be used to help quantify the level of aggressiveness of the inner corner serifs.
    Original languageEnglish
    Title of host publicationIEEE International Conference on Microelectronic Test Structures
    PublisherIEEE Computer Society
    Pages162-167
    Number of pages6
    ISBN (Print)9781424442591
    DOIs
    Publication statusPublished - 14 Apr 2009

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